Equalizer systems are used in optical communications systems, such as in an optical receiver of an optical transceiver module, to remove inter-symbol interference (ISI) contained in a transmitted symbol sequence. A variety of equalizer systems are used for this purpose. Two equalizer systems that are commonly used to remove ISI are decision feedback equalizers (DFEs) and feed-forward equalizers (FFEs). A DFE is an equalizer that uses a bit decision about a previous bit (i.e., post-cursor information) to remove sources of channel degradation (e.g., ISI, dispersion, etc.) contributed by the previous bit from the current bit being decided. Thus, a DFE removes sources of channel degradation associated with past (i.e., previously decided) bits. An FFE is essentially a finite impulse response (FIR) filter that uses a bit decision about a current bit (i.e., pre-cursor information) to remove sources of channel degradation contributed by the current bit from the next bit to be decided.
FIG. 1 illustrates a block diagram of a typical known unclocked, or clockless, FIR filter 2 that operates on a continuous, real-time signal. The FIR filter 2 has N delay cells and N taps, where N is a positive integer that is greater than or equal to 1. Each delay cell 1-N delays the input data signal by a predetermined delay time period. At the end of the respective delay time periods, the respective delayed versions of the input signal are output from the respective delay cells. At respective taps of the FIR filter 2, respective multipliers 4 multiply the respective delayed versions of the input signal by respective tap weights. The products of the multiplication operations are then summed by a summer 7 to produce the filtered output data signal. The delay time period provided by each delay cell is normally set to either 0.5× unit interval (UI) or 1.0×UI, where UI corresponds to the length in time of a bit of the input data signal. In the unclocked FIR filter 2, the delay cells 1-N are analog linear delay cells, which are susceptible to time delay period variations caused by process drift, temperature drift, and/or drift caused by other environmental factors. For this reason, in use applications in which very precise time delay periods are required, the unclocked FIR filter is generally not a suitable solution.
FIG. 2 illustrates a block diagram of a typical known clocked FIR filter 9, which operates on an input data signal in the discrete time domain to produce a filtered output data signal. The FIR filter 9 has N delay cells and N taps, where N is a positive integer that is greater than or equal to 1. Each delay cell 1-N delays the incoming data sample by a predetermined delay time period. At the end of the delay time period, the respective sample values are multiplied by their respective tap weights by multipliers 14. The products of the multiplication operations are then summed by the summer 17 to produce the filtered output sample. As with the unclocked FIR filter 2 shown in FIG. 1, the delay time period for the clocked FIR filter 9 shown in FIG. 2 is normally set to either 0.5UI or to 1.0UI. In the clocked FIR filter 9, the delay cells 1-N are analog/digital delay cells, such as D flip flops, the timing of which is controlled by a clock signal, CLK, output from a clock and data recovery circuit (CDR) (not shown). The bit period, UI, is equal to the period of CLK. Depending on how they are logically configured, the D flip flops latch in the respective sample values on either the rising or the falling edge of CLK and output their respective stored sample values on the next rising or falling edge of CLK. Using clocked flip flops for this purpose enables the delay time periods to be very precisely controlled. Consequently, the clocked FIR filter 9 is a suitable solution in use applications in which the delay time periods need to be very precise and unvarying.
FIG. 3 illustrates a block diagram of a typical known FFE/DFE equalizer 21 that is made up of a linear buffer 22, an FFE 23, a DFE 24, a CDR 25, and a delay locked loop (DLL) 26. The delay time period variations that can result when using an unclocked FIR filter generally have minimal impact on the performance of an FFE equalizer that incorporates the unclocked FIR filter. However, delay time period variations can have a major detrimental impact on the performance of a DFE. For this reason, the DFE 24 incorporates a clocked FIR filter 27, which is an FIR filter of the type shown in FIG. 2. The FFE 23 may incorporate an unclocked FIR 28, such as the FIR filter shown in FIG. 1. The DFE 24 also incorporates a slicer 29 that performs quantization.
In the DFE 24, optimal performance is normally achieved when the time delay periods are equal to 1UI. The approach that is commonly used to achieve precisely 1UI time delay periods in the DFE 24 is as follows. The DLL 26 receives the recovered clock signal output from the CDR 25 and the quantized sample value output from the slicer 29. The DLL 26 properly aligns the recovered clock with the sample value output from the slicer 29. The DLL then provides the aligned clock signal to the clocked FIR filter 27 of the DFE 24. The outputs of the clocked FIR filter 27 and of the unclocked FIR filter 28 are combined by adder 31 to remove sources of channel degradation (e.g., ISI and dispersion) from the signal being input to the DFE 24.
The configuration of the FFE/DFE equalizer 21 shown in FIG. 3 enables very precise time delay periods to be achieved while introducing only a minimal phase delay in the clock signal provided to the first tap of the clocked FIR filter 27. These are key factors in ensuring proper performance of the FFE/DFE equalizer 21. However, due in large part to the need for the clocking circuitry (e.g., the DLL 25 and any clock distribution circuitry), the FFE/DFE equalizer 21 uses relatively complex circuitry, consumes a significant amount die area and dissipates a significant amount of power. In addition, the FFE/DFE equalizer 21 is relatively expensive to manufacture due to circuit complexity and die area.
A need exists for an FFE/DFE equalizer that has very precise timing and high accuracy, and that has relatively low circuit complexity, consumes a relatively small area on the die, and dissipates a relatively small amount of power.